1. Field of the Invention
The present invention relates to a semiconductor logic circuit apparatus, especially to a semiconductor logic circuit apparatus which is capable of holding past input data and of changing the held data according to a switching means.
2. Description of Related Art
FIG. 1 is a circuit diagram showing one construction example of a conventional semiconductor logic circuit apparatus (in the following, to be called a logic circuit apparatus) which is capable of holding past input data and of changing the held data according to a switching means, especially an example in which, as shown, a ratio latch circuit is constructed.
In FIG. 1, the logic circuit apparatus is provided with inverter circuits 1a and 1b, especially the inverter circuit 1b comprising a P-type field effect transistor (hereinafter to be called FET) 1c and an N-type FET 1d. The input terminal of the inverter 1a and the output terminal of the inverter 1b are connected to a node 2a, and the input terminal of the inverter 1b and the output terminal of the inverter 1a are connected to a node 2b. One end of an N-type FET 3 is connected to the node 2a and the other end thereof is connected to a data input terminal 5. A gate of the FET 3 receives control signal through a control terminal 6. The node 2b is also connected to a data output terminal 7.
Next, explanation will be given on the operation of the conventional logic circuit apparatus shown in FIG. 1.
Referring to FIG. 1, explanation will be given, at first, on the operation, for example, of the time when the logic circuit apparatus changes its state from a "0" holding state to a "1" holding state. In this case, a control signal "1" is applied to the gate of the FET 3, the FET 3 becomes conductive, so that the data input terminal 5 and node 2a are electrically connected. The signal at the node 2a is initially "0". The value of input data input from the input terminal 5 is "1", the value at the node 2b is initially "1" and the FET 1d is on until the output of the inverter 1a is changed. Therefore, corresponding to ratio of the FET 3 and FET 1d, the electric potential of the node 2a rises. But, since the FET 3 is N-type and FET 1d is on an electric potential is applied to the input of inverter 1a that is lower that the source potential at input terminal 5 by the threshold Vth of the FET 3. When the electric potential at the node 2a rises until it exceeds the logical threshold of the inverter 1a, the output of the inverter 1a changes to "0", the FET 1a is turned off, and the FET 1c is turned on. As a result, the electric potential of the node 2a rises until it reaches the source potential. After that, when the control signal changes from "1" to "0" and the FET 3 becomes non-conductive, the nodes 2a and 2b hold respective values in the state existing immediately before the change of the control signal at the gate of the FET 3. The data output terminal 7 continues to output the value of the node 2b until the FET 3 is again made conductive.
Next, FIG. 2 is a circuit diagram showing another example of the conventional logic circuit apparatus, especially an example of a ratioless latch circuit.
As shown in FIG. 2, an input terminal of an inverter 1a, one end of an N-type FET 3a and one end of a P-type FET 3b are connected to a node 2a. An input terminal of an inverter 1b and the output terminal of the inverter 1a are connected to a node 2b. The other end of the P-type FET 3b and the output terminal of the inverter 1b are connected to each other. The other end of an N-type FET 3 is connected to a data input terminal 5. A control signal is applied to the gates of the FETs 3a and 3b through a control terminal 6. The node 2b is connected to a data output terminal 7.
Referring to FIG. 2, explanation will be given of operation, for example, at a time when the logic circuit apparatus changes from a "0" holding state to a "1" holding state.
In this case, when control signal "1" is applied to the gates of FETs 3a and 3b, the FET 3a becomes conductive and 3b becomes non-conductive. The data input terminal 5 is electrically connected to the node 2a. The node 2a is electrically disconnected from the output of the inverter 1b. Initially the signal at the node 2a is "0". The new signal of "1" is input to the node 2a from the data input terminal 5. The electric potential of the node 2a rises. Since the FET 3a is N-type, the electric potential at the node 2a only rises to a value lower than the source potential by the threshold Vth of the FET 3a. Even when the electric potential of the node 2a exceeds the logical threshold of the inverter 1a, since the FET 3b is non-conductive as above mentioned, the electric potential of the node 2a does not exceed the value which is lower than the source potential by the threshold Vth of the FET 3a. When control signal changes from "1" to "0", the FET 3a becomes non-conductive and 3b conductive. The nodes 2a and 2b hold their respective values in the state just before the change of the control signal, and the data output terminal 7 continues to output the value of the node 2b until the FET 3 again becomes conductive.
Next, FIG. 3 is a circuit diagram showing another example of a conventional logic circuit apparatus, especially an example of a ratio latch circuit.
The difference between the circuit shown in FIG. 3 from the one shown in FIG. 1 is that ends of an N-type FET 3a are connected respectively with ends of a P-type FET 3b. Complementary signals are connected to the gates of FETs 3a and 3b from control terminals 6a and 6b respectively.
Referring to FIG. 3, explanation will be given of operation when the logic circuit apparatus changes its state from, for example, a "0" holding state to a "1" holding state.
When control signals "1" and "0" are applied to control signal input terminals 6a and 6b respectively of FET 3a and 3b, FETs 3a, 3b become conductive, and the data input terminal 5 is electrically connected to the node 2a. This operation is the same as that of the logic circuit apparatus shown in FIG. 1. Although the FET 1d is on until the output of the inverter 1a changes state, the electric potential of the node 2a rises to a value little lower than the source potential since the FET 3b is P-type. When the electric potential of the node 2a exceeds the logical threshold of the inverter 1a, the output of inverter 1a changes to "0". The FET 1d is turned off and the FET 1c is turned on. The resulting condition is the same as the logic circuit apparatus in FIG. 1. That is, the electric potential of the node 2a rises to the source potential. Also operation when the control signal changes from "1" to "0" is the same as the circuit shown in FIG. 1.
Next, FIG. 4 is a circuit diagram showing a further example of a conventional logic circuit apparatus, especially an example of a ratioless latch circuit.
The difference between the logic circuit apparatus shown in FIG. 4 and the one shown in FIG. 2 is that ends of an N-type FET 3a and ends of a P-type FET 3c are connected respectively to each other. Also, ends of a P-type FET 3b and an N-type FET 3d are connected to each other. A control signal from the control terminal 6a is connected in common to the gates of the FETs 3a and 3b. The control signal from the control terminal 6b is connected in common to the gates of the FETs 3c and 3d. The signal from the control terminal 6a is complimentary to that from 6b.
Referring to FIG. 4, explanation will be given of the operation at a time, for example, when the logic circuit apparatus changes its state from a "0" holding state to a "1" holding state.
When the control signal "1" is applied to the FETs 3a and 3b from the control signal input terminal 6a and the control signal "0" is applied to the FETs 3c and 3d from the control signal input terminal 6b, the FETs 3a and 3c become conductive, and FETs 3b and 3d become non-conductive. While the data input terminal 5 is electrically connected to the node 2a, the node 2a is disconnected from the output of the inverter 1b. The operation is the same as that of the logic circuit apparatus shown in FIG. 2. Since the FETs 3b and 3d are non-conductive and the FET 3b is P-type, the electric potential of the node 2a rises to the source potential. Also the operation when the control signal is changed from "0" to "1" is the same as that shown in FIG. 2.
Conventional semiconductor logic circuit apparatus constructed as above have exhibited the following problems.
In the case of FIG. 1, a change of state from a "0" holding state to a "1" holding state cannot be carried out normally when the source potential is low. That is to say, when the FET 3 becomes conductive by receiving the control signal "1", the electric potential at the node 2a rises according to the ratio of the FET 3 and the FET 1d as above-mentioned. The FET 1d remains on until the output inverter 1a changes from "1" to "0". Here, the electric potential of the node 2a only rises to a value which is lower than the source potential by the threshold voltage Vth because the FET 3 is N-type and the FET 1d is on. Since the source potential dependency of the electric potential of the node 2a is larger than that of logical threshold of the inverter 1a, the electric potential at the node 2a cannot exceed the logical threshold of the inverter 1a when the source potential is low, thereby the inverter 1a cannot operate to produce a "0" output.
In the case of the embodiment of FIG. 2, when the logic circuit apparatus changes its state from "0" holding state to "1" holding state, or when the "0" holding state is prolonged, a feed-through current passes through the inverter 1a. That is to say, when a "1" control signal is applied to the FETs 3a and 3b, the FET 3a becomes conductive and the FET 3b becomes non-conductive. The electric potential of the node 2a rises. Since the FET 3a is N-type and the FET 3b is off, the electric potential at the node 2a only rises to a value which is lower than the source potential by the threshold voltage Vth of the FET 3a. Accordingly, while the node 2a changes its value from "0" to "1", DC feed-through current flows through the inverter 1a. When a "0" holding state is prolonged, the FET 3 b becomes non-conductive to permit the electric potential of the node 2a to float easily from the ground potential of the node 2a. As a result, the electric potential of the node 2a rises to the absolute value of the threshold of the FET 3b, that is, .vertline.Vth.vertline. electric potential, there being the possibility that feed-through current flows through the inverter 1a until the FET 3b becomes conductive.
Next, referring to FIG. 3, explanation will be given on the operation of the time when, for example, the logic circuit apparatus changes its state from a "0" holding state to a "1" holding state. Although the FET 1d is on until the output inverter 1a changes from "0" to "1", the electric potential at the node 2a rises to a value which is a little lower than the source potential since the FET 3b is P-type. Therefore, compared with the example shown in FIG. 1, the inverter 1a is more easily driven. But the FETs 3a and 3b require two kinds of control signals. Moreover, when this first switching means is constructed as part of a group of switching means, the larger the group, the more the number of switching elements increases.
The logic circuit apparatus shown in FIG. 4 has more stability in operation than the ones respectively shown in FIG. 1, FIG. 2 and FIG. 3. However, its use of two, the FETs 3a and 3c two switching means FETs 3b and 3d as CMOS circuits, still requires two kinds of control signals. In addition, when the first switching means consists of a group of switching means, the larger the number thereof, the more the number of the switching elements increases.